1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to scalable charge trapping memory technology adaptable for high speed erase and program operations.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that does not cause cell-to-cell interference like that encountered with floating gate technology, and is expected to be applied for higher density flash memory.
The typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a stack of dielectric material including a tunnel dielectric layer, the charge storage layer, and a blocking dielectric layer. According to the early conventional designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O), and the gate comprises polysilicon (S). The SONOS device is programmed by electron tunneling using one of a number of well-known biasing technologies, and erased by hole tunneling or electron de-trapping. In order to achieve practical operational speeds for the erase operation, the tunneling dielectric layer must be quite thin (less than 30 Å). However at that thickness, the endurance and charge retention characteristics of the memory cell are poor relative to traditional floating gate technology. Also, with relatively thick tunneling dielectric layers, the electric field required for the erase operation also causes electron injection from the gate through the blocking dielectric layer. This electron injection causes an erase saturation condition in which the charge level in the charge trapping device converges on an equilibrium level. See, U.S. Pat. No. 7,075,828, entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”, invented by Lue et al. However, if the erase saturation level is too high, the cell cannot be erased at all, or the threshold margin between the programmed and erased states becomes too small for many applications.
Technology has been investigated to improve the ability of the blocking dielectric layer to reduce electron injection from the gate for the high electric fields needed for erase. See, U.S. Pat. No. 6,912,163, entitled “Memory Device Having High Work Function Gate and Method of Erasing Same,” Invented by Zheng et al., issued 28 Jun. 2005; and U.S. Pat. No. 7,164,603, entitled “Operation Scheme with High Work Function Gate and Charge Balancing for Charge Trapping Non-Volatile Memory”, invented by Shih et al., Shin et al., “A Highly High Reliable SONOS-type NAND Flash Memory Cell with Al2O3 or Top Oxide,” NVSMW, 2003; and Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for a Multi-Gigabit Flash EEPROMs”, IEEE 2005. In the just-cited references, the second Shin et al. article describes a SONOS type memory cell in which the gate is implemented using tantalum nitride and the blocking dielectric layer is implemented using aluminum oxide (referred to as the TANOS device), which maintains a relatively thick tunneling dielectric layer at about 4 nm. The relatively high work function of tantalum nitride inhibits electron injection through the gate, and the high dielectric constant of aluminum oxide reduces the magnitude of the electric field through the blocking dielectric layer relative to the electric field for the tunneling dielectric layer. Shin et al. report a trade-off between the breakdown voltage of the memory cell, the thickness of the aluminum oxide layer and the thickness of the tunneling dielectric layer. With a 4 nm thick silicon dioxide tunneling dielectric in a TANOS device, relatively high erase voltages are proposed in order to achieve erase speeds. An increase in erase speeds would require increasing the voltages applied or decreasing the thickness of the tunneling dielectric layer. Increasing the voltage applied for erase is limited by the breakdown voltage. Decreasing the thickness of the tunneling dielectric layer is limited by issues of charge retention, as mentioned above.
On the other hand, technology has been investigated to improve the performance of the tunneling dielectric layer for erase at lower electric fields. See, U.S. Patent Application Publication No. US 2006/0198189 A1, “Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operating Cells and Arrays,” Invented by Lue et al., publication date Sep. 7, 2006 (describing a “BE-SONOS device”); Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability”, IEEE, December 2005; Wang et al., “Reliability and Processing Effects of the Bandgap Engineered SONOS (BE-SONOS) Flash Memory”, IEEE, May 2007. See also, U.S. Patent Application Publication No. 2006/0261401 A1, entitled “Novel Low Power Non-Volatile Memory and Gate Stack”, by Bhattacharyya, published 23 Nov. 2006.
BE-SONOS technology has been proven to provide excellent performance, overcoming many of the erase speed, endurance and charge retention issues of prior art SONOS type memory. However, the problem of the erase saturation continues to limit operational parameters of the device. Furthermore, as the device sizes shrink, it is expected that erase saturation problems will intensify.
These prior art technologies have emphasized the advantages of high-κ dielectrics, where the dielectric constant κ is greater than 7, like aluminum oxide. The higher dielectric constant can improve performance by enhancing the program and erase speed, improving the threshold voltage window for the cells, and reducing the operating voltage during program and erase by reducing the effective oxide thickness EOT, which is defined as the thickness of the layer scaled by the ratio of the dielectric constant of silicon dioxide to the dielectric constant of the material. However, it is difficult to manufacture high-κ materials like aluminum oxide with high quality. In addition, the charge trapping efficiency of the charge trapping layer can vary with changes in the material of the blocking dielectric. For example, it has been believed that the silicon nitride/silicon oxide interface provides “deep” charge trapping states that resist charge leakage. See, Fujiwara et al., Japanese Patent Application Publication No. 11-040682, published 12 Feb. 1999. Therefore, the use of high-κ materials for the blocking dielectric comes with the trade-off of greater electron de-trapping current than might occur if the lower κ, and higher quality, silicon dioxide were used. Of course, the use of silicon dioxide for the blocking layer results in the problem of high threshold erase saturation, because of the relatively high electric field magnitude in the lower κ material.
One prior art technology that has been attempted to address the issue of high threshold voltage erase saturation is described in Noguchi et al, U.S. Patent Application Publication No. US 2005/0006696, published Jan. 13, 2005. Noguchi et al. proposes a multilayer blocking dielectric structure that includes a secondary charge trapping layer. According to Noguchi et al., by trapping some electrons in the secondary charge trapping layer, the magnitude of the electric field across the blocking dielectric structure is reduced, tending to reduce electron injection to the primary charge trapping layer during an erase operation. In this way, according to Noguchi et al., a lower erase saturation is achieved.
In our commonly owned, and co-pending U.S. patent application entitled CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE, application Ser. No. 11/845,276, filed 27 Aug. 2007, a memory cell is described in which the blocking dielectric layer comprises a high-κ material, such as aluminum oxide, combined with a BE-SONOS tunneling layer. The high-κ blocking dielectric tends to reduce the magnitude of the electric field across it, and therefore reduces electron injection during erase operations based on hole injection from the channel. However, such high-κ materials tend to have defects, requiring that they be made relatively thick to prevent charge leakage or other reliability problems. Our commonly owned, and co-pending U.S. patent application entitled BLOCKING DIELECTRIC ENGINEERED CHARGE TRAPPING MEMORY CELL WITH HIGH SPEED ERASE, application Ser. No. 11/845,321, filed 27 Aug. 2007, describes the use of metal-doped silicon dioxide, taking advantage of the ability to form high quality silicon dioxide films with doping to increase the dielectric constant of the layer.
In general, the problem of electron injection from the gate during an erase bias intended to cause hole tunneling from the channel, which causes erase saturation, arises from the need to have a relatively high electric field in the tunneling layer. This high field in the tunneling layer requires a high field in the blocking layer as well. So, increasing the dielectric constant of the blocking layer tends to improve operation by reducing the magnitude of the electric field within the blocking layer. However, because the high-κ blocking layer must be thicker than would be needed with the standard silicon dioxide layer, the magnitude of the electric field in the tunneling layer is reduced. Therefore, the benefits of these prior techniques are limited by the need to provide a thicker blocking dielectric layer.
U.S. Patent Application Publication No. US 2003/0047755 A1, by Lee et al. proposes the use of a multilayer blocking dielectric layer while trying to minimize the effective oxide thickness of the blocking layer in FIGS. 5-7. In US 2003/0047755A1, the purpose of high-κ blocking oxide is to reduced the effective oxide thickness EOT of the stack between the channel and the gate for a given physical thickness, and to reduce gate injection (see, paragraphs 0034-0042). In order to reduce the EOT according to the concept in US 2003/0047755A1, a multilayer blocking dielectric layer would use a high relative thickness for the high-κ layer relative to the buffer layer. However, a thin buffer oxide layer does not appear to provide substantial gains in retention and reliability without significant increases on the overall actual thickness of the blocking dielectric layer. Furthermore, recent studies of the use of high-κ dielectrics show poor data retention for such cells, as shown for example by FIG. 7, of Chang et al., Reliability Characteristics of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory with Rounded Corner (RC) Structure”, Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint, 18-22 May 2008, Pages: 117-118.
Accordingly, is desirable to provide a new memory technology which is readily manufactured with high quality, and overcomes the reliability and data retention issues of prior art technologies, and that can be applied in very small memory devices.